The present invention relates in general to data communication and, more particularly, to a bit unpacker for parsing out packed data.
In data communication systems, digital data is often transmitted in a compressed format, i.e. encoded to reduce redundant or repetitive information. The multi-bit data words are packed and compressed to remove redundancy and converted into a serial bitstream prior to transmission. The data communication is made more efficient by transmitting fewer total bits. The packed and compressed data must be unpacked and decompressed at the receiving end, and typically converted back to multiple bit words, for use in conventional digital logic.
In the prior art, the bitstream is often arranged on byte or word boundaries for the convenience of the receiving hardware. However, not all of the bits in each byte or word are necessarily used. Therefore, some wasted space occurs with the bitstream arranged on byte or word boundaries.
Other prior art techniques have attempted to use all available space in the bitstream by avoiding sending unused bits. When the packing algorithm finds an unused bit, it skips to the next used bit in the message. On the receiving side, the unpacking process becomes more complex as data boundaries are no longer convenient on a byte or word basis. The meaning of each subsequent bit cannot be determined until the previous bits has been unpacked and interpreted to determine what comes next. The receiving logic often uses a microprocessor executing complex algorithms to perform the unpacking and decoding. The microprocessor solution adds complexity that could be avoided. Once the data is reformed into its original uncompressed fields, the data is available for the end use logic circuitry.
Hence, a need exists to unpack the data as it arrives prior to full decompression.